1. Field of the Invention
This invention relates to a semiconductor nonvolatile memory device and, more particularly, it relates to a semiconductor nonvolatile memory device comprising memory cell blocks such as NAND cell blocks.
2. Description of the Related Art
There are known semiconductor nonvolatile memory devices comprising NAND cell blocks each of which is constituted by a plurality of memory cells. Hereinafter, such a memory device will be referred to as an NAND type EEPROM.
FIGS. 1 through 3B of the accompanying drawings illustrate part of a typical known NAND-type EEPROM, of which FIG. 1 is a circuit diagram and FIG. 2 is a patternized plan view of the part of the device of FIG. 1 while FIGS. 3A and 3B are sectional views taken along lines 3A--3A and 3B--3B of FIG. 2 respectively.
As shown in FIGS. 1 through 3B, a P-type well region 2 is formed on an N-type silicon substrate 1. A NAND cell block is arranged on an element region which is disposed on the well region 2 and surrounded by an element separating insulation film 3, said NAND cell block comprising four memory cells Ma through Md and a pair of selection gate S1, S2. The memory cells Ma through Md comprises respective floating gates 5-1 through 5-4 (or collectively designated by reference numeral 5) made of a first layer polycrystalline silicon film arranged on a first gate insulation film 4 that is formed by thermal oxidation on the well region 2 and respective control gates 7-1 through 7-4 (or collectively designated by reference numeral 7) made of a second layer polycrystalline silicon film arranged on the respective floating gates 5-1 through 5-4.
The control gates 7 of the memory cells are extended along the row to form respective word lines WL1 through WL4. Gate electrodes 7-5, 7-6 of the selection gates S1, S2 are connected to respective selection control lines SGD, SGS. An N-type drain diffusion layer 8 is formed for the NAND cell blocks and connected to a common bit line BL (BL1), whereas an N-type source diffusion layer 9 is formed as a common source line SL for the NAND cell blocks. The selection gate S1 and the memory cell Ma are electrically connected with each other by an N-type diffusion layer 10-1, the memory cell Ma and the memory cell Mb are electrically connected with each other by an N-type diffusion layer 10-2 and so on. The memory cell Md and the selection gate S2 are electrically connected with each other by an N-type diffusion layer 10-5.
A NAND-type EEPROM having the above described configuration operates in a manner as described below.
FIG. 4 of the accompanying drawings is a timing chart illustrating the operation of such a NAND-type EEPROM.
A threshold voltage is established for the memory cells of a NAND cell block by applying a high voltage between the control gates and the well region 2 to force an exchange of electric charges between the floating gates 5 and the well region 2. For example, data may be erased when electrons are discharged form the floating gates 5 to the well region 2 (data "1" status), whereas data may be written when electrons are injected into the floating gates 5 (data "0" status).
Data may be erased out of each of the memory cells. Referring to FIG. 4, if such is the case, the voltage applied to erase data is so biased that, for example, it is 0 V at the control gates (or WL1 through WL4 in FIG. 4), 20 V at the well region (or P-WELL in FIG. 4) and at the substrate (or N-SUB in FIG. 4), 20 V at the first selection gate S1 (or SGD in FIG. 4) and 20 V at the second selection gate S2 (or SGS in FIG. 4). Thus, the threshold voltage level is shifted into negative for the memory cells and may be set to, for example, -2 V.
Data are written in the memory cells sequentially starting from the memory cell close to the source 9 and terminating at the memory cell close to the bit line. As shown in FIG. 4, the voltage applied to write data is again so biased that, for example, it is 20 V at the control gate of a selected memory cell (or WL4 in FIG. 4), an intermediate value of 10 V at the remaining control gates (or WL1 through WL3 in FIG. 4), 0 V at the well region (or P WELL in FIG. 4) and at the substrate (or N SUB in FIG. 4), 10 V at the first selection gate S1 (or SGD in FIG. 4) and 0 V at the second selection gate S2 (or SGS in FIG. 4). The voltage at the bit line (or BL1 in FIG. 4) will show an intermediate value of 10 V when the data is "1" whereas it will be 0 V when the data is "0".
Note that, in the case of FIG. 4, data are written in the memory cells sequentially starting from the memory cell close to the source 9 and terminating at the memory cell close to the bit line.
FIG. 4 also shows the voltage applied to the cell block for retrieving the data stored in it. It will be, for example, 5 V at a selected bit line (or BL1 in FIG. 4) and also 5 V at the selection gates S1 and S2 (or SGD and SGS respectively in FIG. 4). Then, both selection gates S1 and S2 become electrically conductive to connect the NAND cell block to the bit lines BL. Under this condition, only a selected word line (or WL3 in FIG. 4) is held to 0 V, while the remaining word lines (or WL1, WL2 and WL4 in FIG. 4) are set to 5 V. Then, the unselected memory cells M1, M2 and M4 operate as so many transfer gates such that data "0" or "1" is detected depending on the existence or non-existence of electric current on the bit line BL1.
Alternatively, the data stored in each cell block of a NAND-type EEPROM of the type under consideration may be erased collectively. When all the data stored in a cell block are erased collectively, the voltage of the word lines of the remaining NAND cell blocks whose data are not to be erased is held to 20 V, which is the voltage level of the related well regions. Then, the data stored in the NAND cell blocks held under such a biased voltage condition cannot be erased and are securely stored there.
A known NAND-type EEPROM having the above described configuration requires a source line for a pair of NAND cell blocks. Additionally, the source of the device has a large electric resistance because it is made of a diffusion layer. In an attempt to reduce the resistance, a metal line is connected to the source diffusion layer for every several NAND cell blocks. This means that a relatively large space is required to connect the metal line and the source diffusion layer.
Furthermore, a contact is required for each NAND cell block to be connected with a bit line, meaning that a certain additional space is needed to align the metal line and the contact for the bit line.
All these circumstances provide so many difficulties in realizing a high degree of integration and compactness for conventional NAND-type EEPROMs.
Still additionally, if the number of memory cells in a NAND cell block of a conventional NAND-type EEPROM is increased, so many memory cells of a cell block are collectively subjected to data erasure.